Protecting an internal circuit from the threat of ESD damage has been an ongoing challenge for those skilled in the art. Snapback devices are a well-known class of devices that are being adopted in ESD protection circuits. Devices of such a class exhibit a snapback behavior when ESD overstress occurs. FIG. 1 is a diagram showing an I-V curve of a snapback device with a snapback behavior. As illustrated in FIG. 1, when a voltage across the snapback device is below a trigger voltage Vtrig, the snapback device remains cutoff. When the voltage reaches the trigger voltage Vtrig, a p-n junction of the snapback device enters a condition of an avalanche breakdown and triggers a parasitic BJT transistor of the snapback device to turn on and starts conducting a current. Once the snapback device starts conducting a current, the voltage drops to a holding voltage Vhold, and hence, has snapped back before it starts increasing again. The holding voltage Vhold should be higher than an operating voltage Vop of the internal circuit preferably by a safety margin to avoid the snapback device so as to stay turned on when the normal operation is resumed or to latch up. In addition, different internal circuits may require different operating voltages, and therefore, the holding voltage Vhold should be tunable.
In a conventional approach, one or more diodes are connected in series with the snapback device to impose additional voltage drop to increase the holding voltage Vhold. However, the attempt is not only unsuccessful, but also exacerbates the low holding voltage issue described above. FIG. 2 is a diagram showing I-V curves of a single snapback device (shown in dotted line) and a snapback device plus a diode (shown in solid line). As illustrated in FIG. 2, the holding voltage Vh2 of the snapback device in series with a diode is much lower than the holding voltage Vh1 of the single snapback device, indicating that an extra current conducting path has been activated.
In another conventional approach, a guard ring structure is inserted between the one or more diodes and the snapback device whereby holes and electrons flowing in the substrate can be captured, and thereby the extra current conducting path is suppressed from being activated. Though the additional guard ring structure assists the one or more diodes to serve the intended purpose, it may occupy much more layout area for the guard ring structure itself and the extra layout spacing required.
Therefore, it is desirable to provide an ESD protection circuit with a tunable holding voltage that requires less additional layout area.